As integrated circuit devices become more highly integrated and include finer geometries, it can become increasingly important to reduce the size of isolation regions that are used to isolate active devices such as transistors from one another. The initial formation of isolation regions may determine the size of an active region and the process margins for subsequent processing. Accordingly, reduction of the size of the isolation regions is desirable.
LOCal Oxidation of Silicon (LOCOS) is widely used for fabricating isolation regions in integrated circuits. The LOCOS process can be simple. However, in highly integrated devices, such as 256 MB DRAM devices, as the width of the isolation region is reduced, a punchthrough may be caused by "bird's beak" during oxidation. This may reduce the thickness of a field oxide film and may reduce the size of the active regions.
An isolation method may also use a trench, rather than forming a field oxide layer by thermal oxidation. In trench isolation methods, a trench is formed on the integrated circuit device and is filled with an insulating material such as an oxide layer, to thereby form an isolation region that can be smaller than that formed by the LOCOS method. Moreover, problems of the LOCOS method and problems caused by the thermal oxidation can be controlled.
A trench isolation method is disclosed in "A Highly Manufacturable Trench Isolation Process for Deep Submicron DRAMs", IEDM Tech. Digest, pp. 57-60, 1993, by P. Fazan et al. As disclosed, a pad oxide layer and a silicon nitride layer are formed and patterned on an integrated circuit substrate. The integrated circuit substrate is then etched using the patterned silicon nitride layer and pad oxide layer as a mask, to form a trench. Then, a sidewall of the trench is thermally oxidized, and an oxide layer is formed in the trench by chemical vapor deposition. The oxide layer is then planarized by Chemical Mechanical Polishing (CMP). Subsequently, the silicon nitride layer is removed, and an oxide spacer is formed on the sidewall of the oxide layer. The pad oxide layer is then wet etched to complete an isolation layer and to form a gate oxide layer and a gate.
FIG. 1 illustrates fabrication steps for conventional trench isolation methods. As shown in FIG. 1, in a conventional trench isolation method, a pad oxide layer is formed on an integrated circuit substrate, such as a semiconductor substrate, at Block 10. A silicon nitride layer is then formed on the pad oxide layer at Block 12. A photoresist layer is formed on the silicon nitride layer at Block 14. The photoresist layer is patterned by conventional methods to form a photoresist mask pattern.
Continuing with the description of FIG. 1, at Block 16, the silicon nitride layer is patterned using the patterned photoresist as a mask. The photoresist is then removed at Block 18. The silicon nitride layer is then used to form a trench at Block 20. An insulating layer is formed in the trench and on the substrate, to thereby bury the trench, at Block 22. Chemical-mechanical polishing is then used to planarize the trench at Block 24. The silicon nitride layer is then removed at Block 26. The details of conventional trench isolation are well known to those having skill in the art, and need not be described further herein.